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74ALVC38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs
December 2001 Revised March 2005
74ALVC38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs
General Description
The ALVC38 contains four 2-input NAND gates with open drain outputs. This product is designed for low voltage (1.4V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The ALVC38 is fabricated with advanced CMOS technology to achieve high-speed operation while maintaining CMOS low power dissipation.
Features
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD
3.3 ns max for 3.0V to 3.6V VCC 4.2 ns max for 2.3V to 2.7V VCC 6.7 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs s Uses patented Quiet Series noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance:
Human body model ! 2000V Machine model ! 250V
Ordering Code:
Order Number 74ALVC38M 74ALVC38MTC Package Number M14A MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names An , Bn On Description Inputs Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500719
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74ALVC38
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG)
0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 3)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
40qC to 85qC
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 -1.95 2.3 - 2.7 2.7 - 3.6 VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 100 PA 4 mA 6 mA 12mA 24 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3 3.6 3.6 0 3.6 3 -3.6 0 d VI d 3.6V 0 d VO d 3.6V VI VIH VCC or GND, IO VCC 0.6V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 0.2 0.45 0.4 0.7 0.4 0.55 V V V Max Units
r5.0 r10
40 750
PA PA PA PA
'ICC
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74ALVC38
AC Electrical Characteristics
TA Symbol Parameter V CC Min tPHL, tPLH Propagation Delay Bus to Bus 1.1 CL 3.3V r 0.3V Max 3.3 50 pF V CC Min 1.3 2.7V Max 4.2 V CC Min 0.8
40qC to 85qC, RL
500: CL 2.5V r 0.2V Max 3.7 30 pF V CC Min 1.0 1.8V r 0.15V Max 6.7 ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VI VI Outputs Enabled f 0V or VCC 0V or VCC 10 MHz, CL 50 pF Conditions TA VCC 3.3 3.3 3.3 2.5
25qC
Typical 6 7 20 20
Units pF pF pF
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TABLE 1. Values for Figure 1 TEST tPZL, tPLZ SWITCH VL
FIGURE 1. AC Test Circuit TABLE 2. Symbol Vmi Vmo Vx VL VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V 6V 2.7V 1.5V 1.5V VOL 0.3V 6V 2.5V r 0.2V VCC /2 VCC /2 VOL 0.15V VCC*2 1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VCC*2
FIGURE 2. Waveform for Open Drain, Inverting and Non-inverting Functions
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74ALVC38
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74ALVC38 Low Voltage Quad 2-Input NAND Gate with Open Drain Outputs and 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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